1. Field of the Invention
The present invention relates to a liquid crystal display system. In particular, the present invention relates to a liquid crystal display system displaying a color video signal from a personal computer (hereinafter, referred to as a PC) as an image on a high definition liquid crystal display panel. The system suppresses jitter and the like on a display screen caused by the phase shift between a video signal and a synchronizing signal, and the fluctuations of the synchronizing signal; thereby enabling a stable and clear image to be displayed.
2. Description of the Related Art
Processors such as PCs generally use cathode ray tubes (CRTs) as image displays, and video display outputs from PCs are designed for the CRTs.
FIGS. 1 through 3 illustrate a PC. More specifically, FIG. 1 is a view showing an external appearance of the PC. FIG. 2 shows an internal configuration of the PC. FIG. 3 shows a configuration of a connector connecting the PC to a CRT display portion. It is noted that FIG. 3 shows a pin arrangement of a connector for the standard VGA video output standardized by VESA.
A PC 200 includes a PC main body 210 and a CRT display portion 220 displaying a video display signal from the PC main body 210 as an image. The video display output from the PC main body 210 is supplied to the CRT display portion 220 through an analog cable 230. One end of the analog cable 230 is connected to the PC main body 210 through a connector 211 and the other end thereof is connected to the CRT display portion 220.
The PC main body 210 contains a mother board 210a provided with an LSI chip 201 working as a central processing unit (CPU), LSI chips 202 and 203 working as a RAM and a ROM, and an LSI chip 204 working as an input and output device. The PC main body 210 also contains a video board 210b provided with a video signal output portion, or a video signal generating portion (not shown), outputting a video signal for displaying the content processed by the CPU. The video board 210b has a configuration available from makers other than PC makers. The video board 210b is further provided with an LSI chip 205 working as a video memory and LSI chips 206 and 207 working as signal generating portions generating a signal required for displaying an image on the CRT display portion 220.
FIG. 4 is a block diagram illustrating a circuit configuration of a video signal generating portion 20. The video signal generating portion 20 includes a video memory 21 storing digital image data, a screen display control circuit 22 reading the digital image data from the video memory 21 based on a signal from a CPU bus or a local bus, a digital-analog converting circuit (DAC) 23 converting the digital image data into video signals, and a timing signal generating circuit 24 generating various timing signals. An oscillator (not shown) in the timing signal generating circuit 24 generates a signal with a predetermined frequency.
The timing signal generating circuit 24 generates a horizontal synchronizing signal S.sub.h for horizontal synchronization of a video signal and a vertical synchronizing signal S.sub.v for vertical synchronization of the video signal. Furthermore, the timing signal generating circuit 24 is configured so as to generate a timing signal S1 for reading digital images from the video memory 21 and a timing signal S2 for digital-analog conversion. The signals S.sub.h, S.sub.v, S1 and S2 are generated based on the frequency of a signal generated by the oscillator of the timing signal generating circuit 24.
The video memory 21 and the circuits 22 through 24 are realized by the LSI chips 206 and 207 on the video board 210b. The video board 210b is connected to the mother board 210a through a socket (not shown). Three kinds of video signals V.sub.r, V.sub.g, and V.sub.b of red (R), green (G) and blue (B) and the horizontal synchronizing signal S.sub.h and the vertical synchronizing signal S.sub.v are output from the PC main body 210 to the CRT display portion 220 as a video display output through the connector 211 shown in FIG. 1.
In recent years, the allocation of signal pins and the like is relatively standardized. The PC 200 uses a 15-pin D-sub connector shown in FIG. 3 as the connector 211. In a display data channel 1,2 (DDC 1,2) system, 15 pins correspond to respective signals (connector for standard VGA video output). More specifically, pins 1 through 3 correspond to a video red signal, a video green signal, and a video blue signal; pins 6 through 8 correspond to a red return signal, a green return signal, and a blue return signal; pins 11, 12, 4, and 15 correspond to monitor ID bits 0, 1, 2, and 3. A pin 5 corresponds to a test signal, and a pin 10 corresponds to a synchronizing return signal. Pins 13 and 14 correspond to a horizontal synchronizing signal and a vertical synchronizing signal, respectively. The pin 9 is not connected anywhere (NC).
In the case where a video display signal from the PC main body is displayed as an image by a CRT display, a stable image can be obtained by supplying only a horizontal synchronizing signal and a vertical synchronizing signal to the CRT display as synchronizing signals.
FIG. 5 shows a system displaying a video display signal as an image by using a liquid crystal display (or a liquid crystal panel) instead of a CRT display. In this figure, the same components as those in FIG. 1 have the same reference numerals.
A video display signal is supplied from the PC main body 210 to a liquid crystal display apparatus 110 through an analog cable 130. One end of the analog cable 130 is connected to the PC main body 210 through the connector 211. The other end of the analog cable 130 is connected to the liquid crystal display apparatus 110.
A plurality of data signal lines (source lines) 115 and a plurality of scanning signal lines (gate lines) 114 are formed on the surface of a substrate of the liquid crystal display apparatus 110 in such a manner that the signal lines 115 cross the scanning lines 114. A TFT-liquid crystal display device has source lines and gate lines with an insulating layer formed therebetween on one of glass substrates, and TFTs (thin film transistors) connected to pixel electrodes are controlled by the source lines and the gate lines. A common electrode is provided on the other glass substrate via a liquid crystal layer.
The liquid crystal display apparatus 110 includes a data driver 150 for driving the data signal lines 115, a scanning driver 140 for driving the scanning signal lines 114, and a signal processing portion 120 containing a control circuit for controlling a display of the liquid crystal display apparatus 110. The liquid crystal display apparatus 110 also has pixels (or dots) at crossing portions of the data signal lines 115 and the scanning signal lines 114.
An analog-digital converter of the liquid crystal display apparatus 110 converts the video signals into digitized video data. The digitized video data is usually temporarily stored in a buffer memory. The stored video data is read to the scanning signal lines 114 and the data signal lines 115 at a given timing of a timing signal. The frequency of the timing signal is set relatively lower than that of a dot clock signal described later. This is because the flyback period required for the CRT display is not required for the liquid crystal display apparatus. In the liquid crystal display apparatus, the video signals can be displayed even during a period corresponding to the flyback period. More specifically, in the liquid crystal display apparatus, the scanning frequency can be lowered, which makes it easy to satisfy the upper limit frequency conditions of the operation of the drivers.
Furthermore, in order to relax the operation conditions of the drivers, video signals can be stored in a buffer memory divided into two systems or the like, and video signals are supplied to the drivers of the liquid crystal display apparatus from the respective systems of the buffer memory.
In the image display system having the above-mentioned structure, it is required to supply video signals precisely at a given timing to the corresponding pixel P. Therefore, in the liquid crystal display apparatus 110, a dot clock signal representing time information is generated. The dot clock signal is used as a sampling signal for conversion of the video signals by an analog-digital converter (ADC). The dot clock signal is generated only from conventional vertical and horizontal synchronizing signals, considering the compatibility with the CRT display. In general, the dot clock signal is generated by using a phase locked loop (PLL) circuit, a voltage control oscillator (VCO) circuit, and a frequency demultiplier or the like, if required.
FIG. 6 is a block diagram showing a dot clock signal generating circuit 120a provided in the signal processing portion 120 of the liquid crystal display apparatus 110. The dot clock signal generating circuit 120a generates a dot clock signal based on a horizontal synchronizing signal.
The dot clock signal generating circuit 120a includes a frequency demultiplier 12 demultiplying a dot clock signal D.sub.c, a phase comparator 11 comparing the phase of a horizontal synchronizing signal S.sub.h with the phase of the dot clock signal D.sub.c, a filter 13 receiving positive comparison output C.sub.p and a negative comparison output C.sub.n of the phase comparator 11, a capacitor 14, and a VCO 15 generating a dot clock signal D.sub.c with a frequency based on the comparison outputs C.sub.p and C.sub.n. The capacitor 14 is connected to an input terminal of the VCO 15.
The dot clock signal D.sub.c is used as a sampling signal for conversion of the video signals by the ADC. The quality of an image is determined by the preciseness of a timing at which the video signals are sampled. The phase shift, fluctuations, etc. of the dot clock signal with respect to the video signal greatly affects the quality of an image of the liquid crystal display apparatus. More specifically, the phase shift, fluctuations, etc. of the dot clock signal cause blurring and flickering of displayed letters, lines and the like, or make lines look thicker, etc.; thereby greatly degrading a display quality.
Thus, it is required that the frequency and the phase of the dot clock signal be precisely matched with the frequency and the phase of the timing signal of digital-analog conversion of the digital image data on the signal generating side (i.e., on the side of the PC). In order to generate a stable dot clock signal D.sub.c, as described in Japanese Laid-Open Patent Publication No. 7-110667, various alterations should be made in the clock signal generating circuit.
In a high definition liquid crystal display apparatus, the frequency of a dot clock signal is very high, i.e., 1000 to 1500 times that of a horizontal synchronizing signal. Thus, the dot clock signal generating circuit of the liquid crystal display apparatus is required to generate a dot clock signal with a stable oscillation frequency during one horizontal synchronizing period and to exactly respond to a horizontal synchronizing pulse at a high speed. Furthermore, the dot clock signal generating circuit should hold the same phase relationship between the dot clock signal and the timing signal as a sampling signal of a video signal on the PC side with high precision.
With the dot clock signal generating circuit using a PLL circuit and a VCO circuit, it is technically difficult to realize both of the stability for a long period of time and the rapid response.
In the dot clock signal generating circuit shown in FIG. 6, the oscillation frequency of the dot clock signal D.sub.c of the VCO circuit 15 is controlled with a voltage V.sub.c obtained by comparing the phase of the horizontal synchronizing signal S.sub.h with that of a demultiplied signal of the dot clock signal D.sub.c.
The VCO circuit is configured in such a manner that the increase in the voltage V.sub.c results in the increase in an oscillation frequency of the circuit and the decrease in the voltage V.sub.c results in the decrease in an oscillation frequency of the circuit. When the voltage V.sub.c is stable for a longer period of time, the oscillation frequency of the VCO circuit is likely to be stabilized. It is desired that a time constant of the portion generating the voltage V.sub.c is set high in order to stabilize an oscillation frequency. In order to set the time constant high, the capacity of the capacitor 14 is increased.
However, the increase in capacity of the capacitor 14 degrades the response of the VCO circuit. For example, in the case where the PC changes a display mode to change a display state, it will take a long time for a display image to be stabilized. During this period, the display image is unsatisfactory. On the other hand, in the case where the response of the VCO circuit is improved, the stability is not maintained for a long period of time.
When the circuit as described above is actually used, in some cases the switching of the display mode on the PC side results in the change in the horizontal synchronizing frequency by about 20%. Therefore, the dot clock signal generating circuit should be designed in such a manner that the horizontal synchronizing frequency has a certain degree of allowance.
In the case where a dot clock signal is not generated on the liquid crystal display apparatus 110 side based on the horizontal synchronizing signal input from the PC side, it is required to add appropriate signal generating circuit on the PC side in order to supply a dot clock signal from the PC side. However, it is difficult to add terminals for outputting a dot clock signal under the condition that the arrangements of the connector for a signal output and an output signal terminal of the PC are determined. Furthermore, considering the compatibility of the CRT display and the liquid crystal display, it is not effective to change the horizontal synchronizing signal output from the video signal output portion of the PC so as to be suitable for the liquid crystal display.